The present invention relates to a method of producing semiconductor integrated circuits, particularly to circuits having different thickness of epitaxial grown layers and different depths of embedded layers.
Transistors incorporated in the conventional semiconductor integrated circuits are formed in a substantially equalized n-type low impurity density layer. As a result, a limitation is imposed on the range of a controllable characteristic with the result that this has prevented the circuit from being high performance and multifunction. For these reasons, concave portions have been heretofore formed in the n-type low impurity density layer or the depth of the embedded area of the n-type high impurity density, for instance, has been changed. However, these methods according to the prior art have been disadvantageous in the fine work and yield as well as increasing the number of steps in the photolithography, diffusion, the growing steps and in the complexity thereof.
FIG. 1 illustrates a partial sectional view of an integrated circuit for explaining an example of a conventional manufacturing method. In this example, two static induction transistors (SIT) T.sub.1 and T.sub.2 are involved and the thickness of n.sup.- epitaxial growth layers 3 thereof are different. For instance, the SIT T.sub.1 is of the upward type and the source electrode S.sub.1 reaches the surface through an n.sup.+ embedded (buried) layer 2 and an n.sup.+ drawing domain 102. The SIT T.sub.2 is a downward type in which the source electrode S.sub.2 is arranged on the surface side and, in this embodiment, the drain electrode D.sub.2 is drawn out from the surface through an n.sup.+ region forming along an n.sup.+ embedded layer 12, the side wall of the concave portion and the surface. The SIT T.sub.1 is separated from the SIT T.sub.2 by a deep P.sup.+ separating or isolation layer 101 substantially reaching a P type substrate 1. In this example, the thickness of the n.sup.- region of the SIT T.sub.1 is more than that of the SIT T.sub.2 and the example illustrates a so called plane type device in which each of the gate P.sup.+ regions 4 and 14 is formed on the same plane as the plane of the drain n.sup.+ region 5 and the source n.sup.+ region 15. The separation among the elements can be attained by the use of the deep convex portion (depression) reaching the substrate 1, a thick insulating film or the like other than such a PN junction.
FIGS. 2(a)-2(c) illustrate sectional views showing the fabricating process of a conventional integrated circuit. Refering to FIG. 2(a), after n.sup.+ regions 2 and 12 are formed on a P type Si substrate by a selective diffusion process, all of the surface is exposed and an n type growth layer 3 is deposited by the epitaxial growth process. The n.sup.+ embedded layers 2 and 12 rise up toward the growth layer side due to a high temperature treatment at the time of growing and the redistribution of the impurity. A SiO.sub.2 film 6 is formed by oxidizing the surface and a P.sup.+ diffusion layer 101 and an n.sup.+ diffusion layer 102 are selectively formed, respectively. The formation of these diffusion layers 101 and 102 requires a high temperature treatment for a long time to obtain a deep layer. Therefore, the rediffusion in the n.sup.+ embedded layers 2 and 12 is remarkably advanced so that a gentle distribution of the impulity density occurs on the side of the growth layer 3. This causes the increase of capacitance, the insufficient breakdown voltage characteristic or the deterioration of the frequency response characteristic. To obtain the deep diffusion depth, the degree of extension in the transverse direction is approximately equal to two times the thickness of the growth layer and the occupied width of the P.sup.+ separating region 101 and the drawing n.sup.+ region 102 can not be disregarded so that the increase of the integration density is hindered.
In the processes shown in FIG. 2(b), a part of the n type growth layer 3 for the SIT T.sub.2 is selectively etched to be thin, and at the same time a part of the selective etching process for forming a drain drawing region 112 is carried out. FIG. 2(b) shows a sectional view after an oxidation step. Since the etched portion extends in the transversal direction when the selective etching is carried out, this process also prevent the integration density from increasing.
FIG. 2(c) illustrates a sectional view in which gate P.sup.+ regions 4 and 14 of the SIT T.sub.1 and T.sub.2 were formed by the selective diffusion technique. Though it is preferable for lowering the capacitance and increasing a current gain that openings for a gate selective diffusion are small, the fine working for forming a gate opening of SIT T.sub.2 on the bottom surface of the convex portion is very difficult due to the gap between a photomask and the surface. Moreover, due to the convex and the concave portions on the surface, the photo-resist can not be coated with uniform thickness. It sometimes occurs to cut off the resist film at the step portion and there will be a difference of exposure conditions for the upper surface and the bottom surface.
FIG. 2(d) is a sectional view showing that after the depth of the concave portion is increased by the selective etching technique so as to reach the drain n.sup.+ region 12, the oxidation is carried out, an opening is defined in the SiO.sub.2 layer, the selective diffusion is carried out, and the drain n.sup.+ region 5 of the SIT T.sub.1, the source n.sup.+ region 15 of the SIT T.sub.2 and the drain drawing n.sup.+ region 112 are formed. For the selective etching technique for semiconductors, a chemically moist-type etching technique (HF--HNO.sub.3 or a like alkaline substance such as KOH), a dry-type etching technique such as a plasma etching technique, sputtering etching technique or the like, a gas etching technique using a gas such as HCL and so on, can be used. In this case, it is also difficult to define the small openings on the bottom surface and to prevent the resist from cutting off at the step portions. After the above described steps, the steps of defining an opening for a contact, metal evaporation and selective etching for forming wiring are carried out to complete the device. However, due to the concave portions or the convex portions, the metal wiring is liable to cut off at the stepped portions and fine working for the bottom surfaces at the concave portions is difficult.
As described above, even in the fabrication of the SITs which are different in the thickness of n type growth layers 3, the decrease of the integration density, the difficulty of fine working for the bottom surface of the concave portion and the cutting of the resist at the stepped portions are liable to happen due to the increase of the time for heat treatment or the formation of deep concave portions. Such a problem will also occur in the integrated circuit involving junction transistors such as an n channel SIT and a npn bipolar transistor (BJT) or in the integrated circuit requiring growth layers with different thickness such as BJT integrated circuit, FET integrated circuit or the like. In the opposite conductivity type device, such a problem will also occur.